1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular, relates to a semiconductor integrated circuit capable of preventing electrostatic breakdown caused by the electrostatic discharge by the charged device model.
2. Background Art
As the semiconductor integrated circuits becomes finer, and the level of integration advances, a phenomenon called ESD (electro-static discharge) becomes an important issue, because electrostatic breakdown is caused by the electro-static charge. As is well known, three models including a human-body model (HBM), a machine model (MM), and a charged device model (CDM) have been proposed for explaining the generation of the electro-static charge breakdown. The human body model is a model in which the breakdown of the device is caused by the discharge of an electrostatic charge accumulated in a human body to the device when the human body touches the device. The machine model is a model in which the electrostatic breakdown is generated when a machine made of metal and having a higher electric capacitance but a lower discharge resistance is in contact with the device. The evaluations of the human body model and the machine model are carried out by discharging static electricity applied between two test terminals of the device.
The charged device model is a breakdown model in which breakdown is caused by discharge of the electric charge accumulated on the package or the lead frames of the device by, for example, friction through the terminals of the device.
As automatic manufacturing processes advance, semiconductor integrated devices often become defective products because of electrification of the devices according to the charged device model by friction or contact with manufacturing equipment during automated test processes and automated assembly processes for electronic machines. The electrostatic breakdown mechanism by the charged device model (CDM) in the conventional semiconductor integrated circuits and its general measure will be described hereinafter. In FIG. 17, an input/output terminal 302 of a semiconductor integrated circuit 300 is connected with a gate of the MOS transistor 304 which constitutes an internal circuit. The source of the MOS transistor 304 is connected with the ground terminal 308 through the ground wiring 306.
An electrostatic protection element 310 is connected between the input/output terminal 302 and the ground terminal 308 and the input/output terminal 302 for testing the electrostatic breakdown mechanism of the charged device model is connected to connected to ground through a switch 312. The electrostatic protection element 310 is provided in order to protect the MOS transistor 304 which constitute the internal circuit from breaking down when the static electricity is externally applied to the input/output terminal 302. This protection element is provided so as to protect against the breakdown by the human body model or the machine model.
In contrast, in the mechanism of the breakdown by the charged device model, it is assumed that when the potential of an input/output terminal falls to the ground potential, while the device is charged by electrification for some reason, the charge of the device is discharged to the ground through the electrostatic protection element 310. At this time, the electric charge accumulated at the gate of the MOS transistor connected to the input/output terminal 302 as shown in FIG. 17 is discharged to the ground from the input/output terminal 302. The charge accumulated at the gate of the MOS transistor 304 which constitutes the internal circuit, is extremely small when compared to the charge accumulated at the ground line wiring 306, so that this charge at the gate of the MOS transistor 304 is discharged within a extremely short period and the gate potential becomes the ground potential. As a result, a large potential difference is generated between the gate and the source of the MOS transistor of the internal circuit, and dielectric breakdown occurs. The larger the wiring resistance R of the ground potential wiring 306, the easier the dielectric breakdown of the gate of the MOS transistor 304 occurs.
A measure that can be taken to prevent the dielectric breakdown of the gate of the MOS transistor 304 is to provide an electrostatic protection element (a CDM element) 314 close to the gate and the source of the MOS transistor 304 in order to suppress the potential difference between the gate and the source of the MOS transistor below the clamp voltage of the electrostatic protection element 314. It has been a general measure to provide a new electrostatic protection element (the CDM protection element) for preventing the electrostatic breakdown by the charged device model. An example of this type of conventional measure is disclosed, for example, in “Electrical Overstress/Electrostatic Discharge Symposium proceedings, Sep. 27–29, 1988, pp. 220–227.
In contrast, a phenomenon has been observed that the MOS capacitor provided between the source wiring and the ground potential wiring is subjected to the dielectric breakdown. This phenomenon is explained with reference to FIGS. 15 and 16. As shown in FIG. 15, the semiconductor integrated circuit device 201 has an internal circuit 208, and one end of the power source wire 200 for supplying the source voltage is connected to one end of the ground potential wire 202, to which the ground potential is supplied. A MOS capacitor 206 having the function of suppressing the fluctuation of the source voltage to be supplied to the internal circuit is provided between the power source wire 200 and the ground potential wire 202, and the other end of the ground potential wire 202 is connected to the ground terminal 204. In FIG. 15, in order to explain this phenomenon, the ground terminal 204 is connected to ground through the discharge test switch 210.
In the semiconductor integrated circuit device 201′ shown in FIG. 16, the internal circuit 208 is connected with the power source wire 200 and the ground potential wire 202, and the internal circuit 208 comprises a MOS capacitor connected between the power source wire 200 and the ground potential wire 200, and the other end of the ground potential wire 202 is connected to the ground terminal 204. Moreover, the semiconductor integrated circuit device 201′ comprises a input/output terminal 212, which is connected to the ground potential wire 202 through an electrostatic protection element 214. Similar to FIG. 15, the input/output terminal 212 is connected to ground through the discharge test switch 211.
Here, the MOS capacitor 206 is provided in most cases in order to suppress the fluctuation of the source voltage applied to the internal circuit 208.
The charge of the devices 201 and 201′ accumulated by electrification is discharged as follows; the charge accumulated in the semiconductor integrated circuit device 201 is discharged to the ground through the discharge test switch 210 by turning on the discharge test switch 210 from the ground terminal 204, and the charge accumulated in the semiconductor integrated circuit device 201′ is discharged to the ground through the discharge test switch 211 by turning on the discharge test switch 210 from the input/output terminal 212. At this time, in the semiconductor integrated circuit device 201, the electric charge accumulated in a capacitance held by the ground potential wire 202 is discharged from the ground terminal 204 through a switch 210, and the electric charge charged in the capacitance held by the power source wire 200 is discharged through circuit elements connected to the power source wire 200.
In the above case, since the discharge speed of the charge charged in the capacitance held by the ground potential wire 202 from the ground terminal 204 is slower than the discharge speed of the charge charged in the capacitance held by the power source wire 200 from the ground terminal through circuit elements, a potential difference ΔV is generated between both terminals of the MOS capacitor 206. If the potential difference ΔV exceeds the electrostatic breakdown voltage, the MOS capacitor is subjected to electrostatic breakdown.
Similarly, in the semiconductor integrated circuit device 201′, the discharge speed of the charge charged in the ground potential wire 202 from the input/output terminal 212 through the electrostatic protection element 214 is slower than the discharge speed of the charge charged in the power source wire 200 from the input/output terminal 212 through the circuit elements, a potential difference ΔV is generated between both terminals of the MOS capacitor 206. If the potential difference ΔV exceeds the electrostatic breakdown voltage, the MOS capacitor 206 is subjected to the electrostatic breakdown.
The potential difference ΔV between both terminals of the MOS capacitor in the semiconductor integrated circuit device 201′ is smaller by a voltage corresponding to the clamp voltage of the electrostatic protection element 214 than the potential difference in the semiconductor integrated circuit device 201.
Conventional techniques about the effect of electrostatic protection elements provided as measures for coping with the above-described HBM and MM and the wire resistance of the ground potential wire 202 on the withstanding potential for the electrostatic breakdown (ESD) are disclosed in documents concerning semiconductor integrated circuit devices including Japanese Examined Patent Application, Second Publication No. Hei 7-24310, Japanese Patent (Granted) Publication No. 2650276, and Japanese Unexamined Patent Application, First Publication No. Hei 7-183457.
Those inventions differs from the electrostatic breakdown of the semiconductor integrated circuit devices due to the charged device models, which is the subject of the present invention. The electrostatic breakdown due to the charged device model can be simulated by electrostatic discharge tests by discharging the charge accumulated in the charged device through the test terminal.
Japanese Unexamined Patent Application, First Publication No. Hei 7-183457 describes (in the subjects to be solved) a case in which “when an extraordinary voltage having a very rapid rise such as the case of CDM is applied to the input terminal”. However, that application describes only about the breakdown due to HBM and MM, not including breakdown due to CDM.
Thus, since the above described conventional techniques (Japanese Examined Patent Application, Second Publication No. Hei 7-24310, Japanese Patent (Granted) Publication No. 2650276, and Japanese Unexamined Patent Application, First Publication No. Hei 7-183457) do not relate to the CDM which is the breakdown model of the semiconductor integrated circuit of the present invention, the discharge path in the semiconductor integrated circuit of the present invention during electrostatic breakdown differs from those of the conventional integrated circuits. In addition, in contrast to the present application, which used the MOS capacitor provided between the power source wire and the ground potential wire as the element subjected to protection against electrostatic breakdown, the conventional techniques make use of the gate of the MOS transistor located in between the input/output terminals and the ground potential wire.